Master Slave D Flip Flop – Positive or Negative Edge Triggered? | allthingsvlsi
File:Edge triggered D flip flop with set and reset.svg - Wikimedia Commons
D Type Flip-flops
flipflop - Explanation of Edge Triggered D type flip flop triggered at positive edge of the clock pulse cycle (from Morris Mano Book)? - Electrical Engineering Stack Exchange
VLSI SoC Design: Dual-Edge Triggered Flip Flop
Flip-Flops and Registers
digital logic - Why is D flip-flop positive edge triggered instead of level triggered? - Electrical Engineering Stack Exchange